1. Field of the Invention
The present invention relates to a general input/output (I/O) control, and to a common input/output terminal control circuit in a device having a common input/output terminal such as a CPU (Central Processing Unit) and the like.
2. Description of the Related Art
Conventionally, when a circuit is configured in which two or more functions can be selected for one general I/O pin, a method of switching signals using a selector is employed.
FIG. 1A shows a configuration example of a conventional common input/output terminal control circuit as above. This control circuit comprises circuits 11 and 12, selectors 13 and 14, a latch circuit (register) 15, and a three-state-buffer 16, and performs a control such that the two circuits 11 and 12 use an I/O pin (not shown) in common provided on the output side of the three-state-buffer 16.
The circuits 11 and 12 respectively have different functions. The circuit 11 outputs a control signal dir1 specifying whether the direction of the I/O pin is the input or the output in accordance with the operation state of the circuit 11, and outputs a data signal data1 when the direction is the output. Similarly, the circuit 12 outputs a control signal dir2 specifying the direction of the I/O pin and a data signal data2.
The latch circuit 15 is configured of a flip flop for example, and latches a selection signal sel_data for switching the selectors 13 and 14, and outputs the signal as a selection signal sel.
The selector 13 selects data1 when the selection signal sel is High (logic “1”), selects data2 when the selection signal sel is Low (logic “0”) and outputs the selected data signal as sw_data.
The selector 14 selects dir1 when the selection signal sel is the logic “1”, and selects dir2 when the selection signal sel is the logic “0” in order to output the selected control signal as sw_dir. This control signal sw_dir is input to an enable terminal of the three-state-buffer 16 with a negative logic, and indicates that the direction of the I/O pin is the input with the logic “1”, and indicates that the direction of the I/O pin is the output with the logic “0”.
When the control signal sw_dir is the logic “1”, the three-state-buffer 16 is in a high impedance state (input state) z, and the signal input from the I/O pin is transferred to the circuit 11 or the circuit 12 via a signal path (not shown). Also, when the control signal sw_dir is the logic “0”, the three-state-buffer 16 is in an output state, and outputs the data signal sw_data to the I/O pin as outdata.
The Patent Document 1 below discloses a common terminal control device which realizes a switching of terminals even when software for the switching of terminals is not activated.
Patent Document 1
Japanese Patent Application Publication No. 2004-192051
The above conventional common input/output terminal control circuit has problems below.
When the circuit configuration of FIG. 1A is employed, there is a probability that a hazard output occurs when switching between the circuits 11 and 12. FIG. 1B and FIG. 1C show timing charts of patterns of this hazard output.
The latch circuit 15 operates in accordance with a clock signal clk, and latches the selection signal sel_data on a rising edge of the clock signal, and outputs the latched signal as the selection signal sel. Accordingly, when the selection signal sel_data is switched from the logic “1” to the logic “0” at a time t1, the selection signal sel is switched from the logic “1” to the logic “0” at a time t2 which is posterior to the time t1 by one cycle.
First, it is assumed that the selection signal sel is switched from the logic “1” (circuit 11) to the logic “0” (circuit 12) at the time t2, and thereafter, the control signal sw_dir is switched from the logic “0” (output) to the logic “1” (input) at a time t3 posteriorly to the change of the data signal sw_data, as shown in FIG. 1B. In this case, during a period T between the time t2 and the time t3, the hazard output occurs.
Next, it is assumed that the selection signal sel is switched from the logic “1” to the logic “0” at the time t2, and thereafter, the control signal sw_dir is switched from the logic “1” to the logic “0” prior to the change of the data signal sw_data at the time t3, as shown in FIG. 1C. Also in this case, during the period T, the hazard output occurs.
A CPU chip manufactured in recent years employs a configuration in which a general I/O pins that can be applied to various usages are provided, and a signal to be connected to a particular I/O pin is selected by means of software, as a result of consideration of a limitation on the number of the I/O pins and generalization.
FIG. 1D shows a configuration example of a common input/output terminal control circuit in the CPU chip as above. A CPU 21 of FIG. 1D comprises an internal register 31, a peripheral circuit 32, a selector 33, and an I/O buffer 34. An external I/O pin 22 is connected to a High level (VDD) via a load circuit 23, and is used for a signal input to the CPU 21 and a signal output from the CPU 21.
In the above case, the internal register 31 and the peripheral circuit 32 respectively correspond to the circuit 11 and the circuit 12 of FIG. 1A. The selector 33 corresponds to the selectors 13 and 14. The I/O buffer 34 corresponds to the three-state-buffer 16.
In a default (reset) state, the selector 33 always selects the internal register 31, and the I/O buffer 34 is in an input state. In this state, if the connection source of the I/O pin 22 is switched from the internal register 31 to the peripheral circuit 32 simply by means of software, there is a probability that the hazard output to the connection destination occurs.
When the connection is switched from the internal register 31 to the peripheral circuit 32, the control signal sw_dir is switched from the logic “1” to the logic “0”, and the I/O buffer 34 is switched from the input state to the output state.
When the internal register 31 is selected, the I/O pin 22 is pulled up to the High level by the load circuit 23, therefore, the data signal outdata is logic “1”. In this state, the connection is switched to the peripheral circuit 32, the output data signal data2 of the peripheral circuit 32 is also the logic “1”, accordingly, the data signal outdata should not become the logic “0” even once. However, due to an internal delay, there is a probability that the hazard output of the logic “0” occurs instantaneously during the period T.
When the connection destination of the I/O pin 22 is a clock terminal or a write enable terminal of a circuit, the circuit operates on a rising edge of a signal, which has caused malfunction of the connection destination circuit. In order to prevent such a hazard output, suitable sequences have been prepared by means of software in the conventional techniques.
In the example of FIG. 1D, it is possible to prevent the hazard output during the period T by changing the output data value of the internal register 31 from the logic “0” to the logic “1” prior to switching of the connection to the peripheral circuit 32, and thereafter using the selector 33 for switching, as shown in FIG. 1F.
However, the number of the I/O pins in the CPU chip tends to increase as the generalization advances, software control steps and check steps of the software sequences increase, and an automation of hazard cancellation is desired.